Job Title: Digital Design Platform Validation Engineer
Platform Validation Engineer is responsible for validating the industry leading SoC implementation products and flow solutions, including “Design Compiler NXT”, “IC Compiler II”, “Formality” and next generation RTL to GDS Digital Design Platform “Fusion Compiler”.
Under this role, a Platform Validation engineer will
– Study and understand customer requirements and R&D functional specifications, design and execute testing plan to validate new features (new functions, Performance/Power/Area improvements, Advanced node 5nm/3nm enablement etc.)
– Using real top-tier customer designs and/or creating new designs to ensure the quality of new features.
– Debug and identify the root causes of functionality issues, flow issues including complicated PPA (Performance/Power/Area) issues in RTL2GDS design flow.
– Analyze customer issues and customer usage/flow, propose coverage improvement plan and enhancement requests to improve the products.
– Design and develop validation solutions/products in Python, C/C++, Perl, Tcl, etc. to improve the testing efficiency and solve complicated EDA software testing challenges such as Machine Learning based testing automation, PPA big data handling etc.
– BS/MS in EE, Microelectronics, CS or relevant （也欢迎2019应届毕业生）
– Self-motivated, good team worker and great learner
– Good verbal and written communication skills in both Chinese and English
– Passionate in learning and supporting new evolving technologies – 5nm/3nm, low power design, 3D IC, machine learning, cloud, data mining etc.
– Experience in SoC design or CAD – Verification, Synthesis, Test, Place & Route, STA, Physical Verification, is a strong plus
– Experience in software testing & software testing automation is a strong plus
– Knowledge and experience in one or more of the following CS fields is a strong plus:
· Programming language (C/C++, Shell, TCL, Perl, Python etc.)
· Unix/Linux operating system